1. Field of the Invention
The present invention relates to semiconductor fabrication, and in particular to a method of checking overlay registration between every two reticle patterns for photolithography.
2. Description of the Related Art
Each lithography step uses a pattern referred to as a layer, such as a(n) patterned conductive layer, semiconductor layer or insulating layer. In order to make semiconductor devices, each photolithography reticle or mask corresponding to a certain structural pattern must be aligned with the semiconductor substrate for overlay registration before exposure.
Conventionally, corresponding alignment marks or features are set on a semiconductor substrate, i.e. a wafer, and the reticle respectively for alignment. Often alignment marks are included in other layers, as the original alignment marks may be obliterated as processing progresses. It is important for each alignment mark on the wafer to be labeled so it may be identified, and for each pattern to specify the alignment mark (and the location thereof) to which it should be aligned. By providing the location of the alignment mark, it is easy to locate the correct feature in a short time. Each layer should have an alignment feature so that it may be registered to the rest of the layers.
Generally, reticle providers usually provide registration specifications for patterns on the reticles. The exposure is performed by aligning the alignment marks directly. FIG. 1 shows a conventional alignment for exposure between a reticle pattern and a wafer. Four alignment marks 12 are disposed on a wafer 10. Four alignment marks 22 on four corners of an exposure pattern 20 on a reticle are positioned to align with the four alignment marks 12, thereby ensuring the pattern 20 is transferred precisely to the predetermined area on wafer 10.
During the exposure, alignment between the reticle pattern 20 and the wafer 10 is accomplished by alignment marks thereon. However, inherent errors within the reticle pattern 20 cannot be adjusted by the exposure alignment. For semiconductor devices requiring multi-level alignment, inherent error addition between two continuous or discontinuous layer patterns may exceed the original specification. Due to shrinking feature sizes, the tolerances for overlay registration of the reticle pattern to the wafer are also reduced.
Conventionally, alignment registration is inspected by preparing thin sections of the testing layers formed on a wafer and viewing by an X-SEM (X-ray scanning electron microscope). FIG. 2 is a profile of an X-SEM section, showing the overlay registration between three layers. The disadvantage of X-SEM sections is they can only show the overlay registration of certain cross-sections of the wafer, not deviations of the alignment in a whole picture. In addition, when CD-SEM is utilized for inspection, designed to inspect critical dimension (CD) for semiconductor devices, the conventional bottom anti-reflection coating (BARC) widely used for photolithography improvement interferes with the detection signals from CD-SEM, thereby causing difficulty in viewing the overlay registration by CD-SEM